C3Subtitles: 32c3: A Free and Open Source Verilog-to-Bitstream Flow for iCE40 FPGAs
back

A Free and Open Source Verilog-to-Bitstream Flow for iCE40 FPGAs

If you suspend your transcription on amara.org, please add a timestamp below to indicate how far you progressed! This will help others to resume your work!

Please do not press “publish” on amara.org to save your progress, use “save draft” instead. Only press “publish” when you're done with quality control.

Video duration
00:59:29
Language
English
Abstract
Yosys (Yosys Open Synthesis Suite) is an Open Source Verilog synthesis and verification tool.

Project IceStorm aims at reverse engineering and documenting the bit-stream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bit-stream files, including a tool that converts iCE40 bit-stream files into behavioral Verilog. Currently the bitstream format for iCE40 HX1K and HX8K is fully documented and supported by the tools.

Arachne-PNR is an Open Source place&route tool for iCE40 FPGAs based on the databases provided by Project IceStorm. It converts BLIF files into an ASCII file format that can be turned into a bit-stream by IceStorm tools.

This three projects together implement a complete open source tool-chain for iCE40 FPGAs. It is available now and it is feature complete (with the exception of timing analysis, which is work in progress).

No description available.

Talk ID
7139
Event:
32c3
Day
1
Room
Hall 1
Start
4 p.m.
Duration
01:00:00
Track
Hardware & Making
Type of
lecture
Speaker
Clifford Wolf
0.0% Checking done0.0%
0.0% Syncing done0.0%
29.1% Transcribing done29.1%
70.9% Nothing done yet70.9%

English: Transcribed until

Last revision: 2 years, 6 months ago