Clifford Wolf

Infos

Event(s):
35th Chaos Communication Congress, 34. Chaos Communication Congress, 33. Chaos Communication Congress, 32. Chaos Communication Congress
Language(s):
English
Track(s):
Hardware & Making, Resilience
Links:
Twitter
Website

Statistics

English
157.6 wpm
904.7 spm
15.5% Checking done15.5%
0.0% Syncing done0.0%
9.2% Transcribing done9.2%
75.3% Nothing done yet75.3%


The nextpnr FOSS FPGA place-and-route tool

Event
35c3
Date
Dec. 28, 2018, 1:10 p.m.
Language
English
Video-Duration
00:46:51
Speaker
Clifford Wolf
en:
0.0% Checking done0.0%
0.0% Syncing done0.0%
0.0% Transcribing done0.0%
100.0% Nothing done yet100.0%
Last revision: 7 years ago


End-to-end formal ISA verification of RISC-V processors with riscv-formal

Event
34c3
Date
Dec. 27, 2017, 11:45 a.m.
Language
English
Video-Duration
00:29:05
Statistics
Average whole talk
150.3 wpm
863.4 spm
Average while speakers speak
157.6 wpm
904.7 spm
Speaker
Clifford Wolf
157.6 wpm
904.7 spm
en:
100.0% Checking done100.0%
0.0% Syncing done0.0%
0.0% Transcribing done0.0%
0.0% Nothing done yet0.0%
Last revision: 6 years ago


Formal Verification of Verilog HDL with Yosys-SMTBMC

Event
33c3
Date
Dec. 28, 2016, 4:15 p.m.
Language
English
Video-Duration
00:52:24
Speaker
Clifford Wolf
en:
0.0% Checking done0.0%
0.0% Syncing done0.0%
0.0% Transcribing done0.0%
100.0% Nothing done yet100.0%
Last revision: 5 years ago


A Free and Open Source Verilog-to-Bitstream Flow for iCE40 FPGAs

Event
32c3
Date
Dec. 27, 2015, 3 p.m.
Language
English
Video-Duration
00:59:29
Speaker
Clifford Wolf
en:
0.0% Checking done0.0%
0.0% Syncing done0.0%
29.1% Transcribing done29.1%
70.9% Nothing done yet70.9%
Last revision: 9 years, 7 months ago