C3Subtitles: 35c3: LibreSilicon
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LibreSilicon

Decentralizing semiconductor manufacturing

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Video duration
01:00:12
Language
English
Abstract
While a lot of projects are currently developing their own processors, mostly as open source in Verilog, VHDL or even Chisel, we miss the free process that actually manufactures these chips. So we're developing the "Libre Silicon" project, a portable semiconductor manufacturing process and technology, using only free and open source tools: We would like to introduce the project, who we are, what we are doing and where we are now.

The manufacturing is proprietary and has vendor lock-ins with triple NDAs – one for the <b>process development kit</b> (PDK), the technology itself; – one for the Standard Cell Library you can use to synthesize your RTL; – and even another one for the details of all purchase commitments.

Our purpose is a free and open, community based silicon manufacturing process (<a href="https://github.com/libresilicon/process">GitHub link</a>) without any NDAs, a Standard Cell Library (<a href="https://github.com/chipforge/StdCellLib">GitHub link</a>) not only for that process as well as a suitable, refurbished, new-written open source tool chain QtFlow (<a href="https://github.com/leviathanch/qtflow">GitHub link</a>).

During the last couple of months we already developed the first free 1µm process and are now close to manufacturing a first test wafer (<a href="https://github.com/libresilicon/PearlRiver">GitHub link</a>). Even though 1µm does not sounds very ambitious, this process node is still quite well documented in text books, robust and 5 Volt-tolerant.

Once we get a hang on this, the machinery park in the clean room allows us to shrink down to 500nm and less.

Talk ID
9410
Event:
35c3
Day
1
Room
Eliza
Start
12:50 p.m.
Duration
01:00:00
Track
Hardware & Making
Type of
lecture
Speaker
Andreas Westerwick
hsank
leviathan
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English: Transcribed until

Last revision: 2 weeks ago