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This talk introduces the algorithms used for placement and routing of digital integrated circuits.
The talk does \*not\* cover:
\* high-level circuit design (The art of creating meaningful circuits. Often done with languages like Verilog, VHDL, SpinalHDL, Chisel, Amaranth, etc )
\* logic synthesis (Converts the high-level description into a graph-like circuit description, called netlist)
Place-and-route refers to the transformation of a graph-like circuit description (netlist) into a geometrical representation of the circuit (layout).
The netlist is typically produced by logic synthesis. The netlist consists of many sub-circuits, so called "standard-cells" but also "macro cells".
Standard-cells implement simple logic functions such as inverters, logical "and", "nand", "xor", and storage elements.
The netlist may also import larger pre-compiled macro cells such as SRAM blocks.
For a physical implementation of the circuit, the sub-circuits need to be placed on the chip surface and need to be connected (routed) using metal wires.
Transforming the netlist into a layout typically requires the following input data:
\* A netlist of the circuit, of course.
\* A set of constraints: For example the desired clock frequency and area of the circuit.
\* Design rules: A set of constraints required for successful fabrication. This typically involves geometrical constraints such as minimum width and spacing of metal wires.
\* A standard-cell library: This is a set of building-blocks usually used to assemble the circuit. The library contains the geometrical layout of the standard-cells and also information about their timing behavior.
Then the following steps convert the input data into a layout:
\* IO-planning: Decide where to put the input and output pins of the circuit.
\* Floor-planning: Decide how to geometrically arrange various parts of a larger system.
\* Power distribution: Insert regular rows of metallic power-rails which supply the standard-cells with energy
\* Global placement: Decide where to roughly place the standard-cells such that the wiring will short and possible
\* Tie-cell insertion: Provide constant 0 and 1 signals, where needed.
\* Clock-tree synthesis: Storage elements typically need a clock-signal. Often the clock signal needs to be distributed to a large number of storage elements.
\* Detail placement: Do fine-tuning, such as snapping the standard-cells to a grid
the signal propagation delay from the clock source to the storage elements should be more-or-less equally distributed.
\* Optimizations to meet timing requirements: Some signals might be too slow or to fast. There's a variety of techniques to improve this, such as amplifying signals with buffers.
\* Routing: The placed cells need to be connected with metal wires.
\* Filler insertion: fill unused space for example with capacitors to stabilize the supply voltage
\* Verification: Make sure all constraints are met. Otherwise, try to fix the circuit and repeat above steps in order to converge to a valid solution.
This talk will focus on a widely used algorithm for global placement and introduces basic principles of routing algorithms.